12 search results - page 1 / 3 » The MAJC Architecture: A Synthesis of Parallelism and Scalab... |
MICRO
2000
IEEE
13 years 4 months ago
2000
IEEE
SBCCI
2003
ACM
13 years 10 months ago
2003
ACM
Networks-on-Chip (NoCs) interconnection architectures to be used in future billion-transistor Systems-on-Chip (SoCs) meet the major communication requirements of these systems, of...
ASPDAC
1995
ACM
13 years 8 months ago
1995
ACM
Abstract — A datapath synthesis system (DPSS) for the reconfigurable datapath architecture (rDPA) is presented. The DPSS allows automatic mapping of high level descriptions onto...
ASAP
1996
IEEE
13 years 9 months ago
1996
IEEE
A datapath synthesis system (DPSS) for a bus-based wavefront array architecture, called rDPA (reconfigurable datapath architecture), is presented. An internal data bus to the arra...
ISCAS
2008
IEEE
13 years 11 months ago
2008
IEEE
Abstract— We present the concepts and realization of a highly parallelized decoder architecture for LDPC convolutional codes and tailbiting LDPC convolutional codes. This archite...