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» The Sizing Rules Method for Analog Integrated Circuit Design
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DAC
2003
ACM
13 years 11 months ago
Performance trade-off analysis of analog circuits by normal-boundary intersection
We present a new technique to examine the trade-off regions of a circuit where its competing performances become “simultaneously optimal”, i.e. Pareto optimal. It is based on ...
Guido Stehr, Helmut E. Graeb, Kurt Antreich
DAC
2005
ACM
13 years 8 months ago
Performance space modeling for hierarchical synthesis of analog integrated circuits
Automated analog sizing is becoming an unavoidable solution for increasing analog design productivity. The complexity of typical analog SoC subsystems however calls for efficient ...
Georges G. E. Gielen, Trent McConaghy, Tom Eeckela...
ICCAD
2008
IEEE
107views Hardware» more  ICCAD 2008»
14 years 20 days ago
Importance sampled circuit learning ensembles for robust analog IC design
This paper presents ISCLEs, a novel and robust analog design method that promises to scale with Moore’s Law, by doing boosting-style importance sampling on digital-sized circuit...
Peng Gao, Trent McConaghy, Georges G. E. Gielen
DATE
2009
IEEE
134views Hardware» more  DATE 2009»
14 years 29 days ago
Massively multi-topology sizing of analog integrated circuits
This paper demonstrates a system that performs multiobjective sizing across 100,000 analog circuit topologies simultaneously, with SPICE accuracy. It builds on a previous system, ...
Pieter Palmers, Trent McConaghy, Michiel Steyaert,...
ASPDAC
2007
ACM
101views Hardware» more  ASPDAC 2007»
13 years 10 months ago
Robust Analog Circuit Sizing Using Ellipsoid Method and Affine Arithmetic
-- Analog circuit sizing under process/parameter variations is formulated as a mini-max geometric programming problem. To tackle such problem, we present a new method that combines...
Xuexin Liu, Wai-Shing Luk, Yu Song, Pushan Tang, X...