100 search results - page 2 / 20 » The Sizing Rules Method for Analog Integrated Circuit Design |
DAC
2003
ACM
13 years 11 months ago
2003
ACM
We present a new technique to examine the trade-off regions of a circuit where its competing performances become “simultaneously optimal”, i.e. Pareto optimal. It is based on ...
DAC
2005
ACM
13 years 8 months ago
2005
ACM
Automated analog sizing is becoming an unavoidable solution for increasing analog design productivity. The complexity of typical analog SoC subsystems however calls for efficient ...
ICCAD
2008
IEEE
14 years 20 days ago
2008
IEEE
This paper presents ISCLEs, a novel and robust analog design method that promises to scale with Moore’s Law, by doing boosting-style importance sampling on digital-sized circuit...
DATE
2009
IEEE
14 years 29 days ago
2009
IEEE
This paper demonstrates a system that performs multiobjective sizing across 100,000 analog circuit topologies simultaneously, with SPICE accuracy. It builds on a previous system, ...
ASPDAC
2007
ACM
13 years 10 months ago
2007
ACM
-- Analog circuit sizing under process/parameter variations is formulated as a mini-max geometric programming problem. To tackle such problem, we present a new method that combines...