Abstract. In this paper it is demonstrated how two issues from the area of testing electronic components can be merged and solved by means of a genetic algorithm. The two issues ar...
A technique is proposed to reduce the peak power consumption of sequential circuits during test pattern application. High-speed computation intensive VLSI systems, as telecommunica...
Test data volume and scan power are two major concerns in SoC test. In this paper we present an alternative run-length coding method through scan chain reconfiguration to reduce b...
Power and energy consumption of digital systems may increase significantly during testing. This extra power consumption due to test application may give rise to severe hazards to ...
—Wafer-level test during burn-in (WLTBI) is a promising technique to reduce test and burn-in costs in semiconductor manufacturing. However, scan-based testing leads to significa...