265 search results - page 1 / 53 » The Use of Genetic Algorithm to Reduce Power Consumption dur... |
ICES
2010
Springer
13 years 3 months ago
2010
Springer
Abstract. In this paper it is demonstrated how two issues from the area of testing electronic components can be merged and solved by means of a genetic algorithm. The two issues ar...
EVOW
1999
Springer
13 years 9 months ago
1999
Springer
A technique is proposed to reduce the peak power consumption of sequential circuits during test pattern application. High-speed computation intensive VLSI systems, as telecommunica...
ATS
2004
IEEE
13 years 8 months ago
2004
IEEE
Test data volume and scan power are two major concerns in SoC test. In this paper we present an alternative run-length coding method through scan chain reconfiguration to reduce b...
ISQED
2000
IEEE
13 years 9 months ago
2000
IEEE
Power and energy consumption of digital systems may increase significantly during testing. This extra power consumption due to test application may give rise to severe hazards to ...
VTS
2008
IEEE
13 years 11 months ago
2008
IEEE
—Wafer-level test during burn-in (WLTBI) is a promising technique to reduce test and burn-in costs in semiconductor manufacturing. However, scan-based testing leads to significa...