37 search results - page 1 / 8 » The Use of Runtime Reconfiguration on FPGA Circuits to Incre... |
JUCS
2007
13 years 4 months ago
2007
: This article presents an architecture that encrypts data with the AES algorithm. This architecture can be implemented on the Xilinx Virtex II FPGA family, by applying pipelining ...
GLVLSI
2005
IEEE
13 years 10 months ago
2005
IEEE
This paper addresses a pipelined partial rolling (PPR) architecture for the AES encryption. The key technique is the PPR architecture, which is suitable for FPGA implementation. U...
FPGA
2006
ACM
13 years 8 months ago
2006
ACM
In this paper, we propose a technique to flexibly implement genetic algorithms for various problems on FPGAs. For the purpose, we propose a basic architecture for GA which consist...
CHES
2003
Springer
13 years 8 months ago
2003
Springer
Abstract. Performance evaluation of the Advanced Encryption Standard candidates has led to intensive study of both hardware and software implementations. However, although plentifu...
IPPS
2006
IEEE
13 years 11 months ago
2006
IEEE
Control algorithms implemented directly in hardware take advantage of parallel signal processing. Furthermore, implementing controller functionality in reconfigurable hardware fac...