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    FPGA
    2006
    ACM
    195views FPGA» more  FPGA 2006»
    An adaptive Reed-Solomon errors-and-erasures decoder
    13 years 9 months ago
    An adaptive Reed-Solomon errors-and-erasures decoder
    Download  www.ecs.umass.edu
    The development of Reed-Solomon (RS) codes has allowed for improved data transmission over a variety of communication media. Although Reed-Solomon decoding provides a powerful def...
    Lilian Atieno, Jonathan Allen, Dennis Goeckel, Rus...
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    FPGA
    2004
    ACM
    120views FPGA» more  FPGA 2004»
    Flexibility measurement of domain-specific reconfigurable hardware
    13 years 11 months ago
    Flexibility measurement of domain-specific reconfigurable hardware
    Download  www.ee.washington.edu
    Traditional metrics used to compare hardware designs include area, performance, and power. However, these metrics do not form a complete evaluation of reconfigurable hardware. For...
    Katherine Compton, Scott Hauck
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    JCP
    2008
    119views more  JCP 2008»
    Performance Comparisons, Design, and Implementation of RC5 Symmetric Encryption Core using Reconfigurable Hardware
    13 years 6 months ago
    Performance Comparisons, Design, and Implementation of RC5 Symmetric Encryption Core using Reconfigurable Hardware
    Download  www.academypublisher.com
    With the wireless communications coming to homes and offices, the need to have secure data transmission is of utmost importance. Today, it is important that information is sent con...
    Omar S. Elkeelany, Adegoke Olabisi
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    JIRS
    2007
    108views more  JIRS 2007»
    Task-based Hardware Reconfiguration in Mobile Robots Using FPGAs
    13 years 6 months ago
    Task-based Hardware Reconfiguration in Mobile Robots Using FPGAs
    Download  hotnsour.ou.edu
    This paper presents a methodology for the realization of intelligent, task-based reconfiguration of the computational hardware for mobile robot applications. Task requirements are ...
    Sesh Commuri, V. Tadigotla, L. Sliger
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    DAC
    2008
    ACM
    145views Computer Architecture» more  DAC 2008»
    Enhancing timing-driven FPGA placement for pipelined netlists
    14 years 7 months ago
    Enhancing timing-driven FPGA placement for pipelined netlists
    Download  www.ee.washington.edu
    FPGA application developers often attempt to use pipelining, Cslowing and retiming to improve the performance of their designs. Unfortunately, such registered netlists present a f...
    Kenneth Eguro, Scott Hauck
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