338 search results - page 2 / 68 » The design and implementation of formal monitoring technique... |
TCAD
2008
13 years 4 months ago
2008
The quality and the correctness of software is often the greatest concern in electronic systems. Formal verification tools can provide a guarantee that a design is free of specific...
DAC
2009
ACM
14 years 6 months ago
2009
ACM
Continuously shrinking feature sizes result in an increasing susceptibility of circuits to transient faults, e.g. due to environmental radiation. Approaches to implement fault tol...
ICCD
2004
IEEE
14 years 1 months ago
2004
IEEE
Formal and dynamic (simulation, emulation, etc.) verification techniques are both needed to deal with the overall challenge of verification. Ideally, the same specification/tes...
ICCD
2004
IEEE
14 years 1 months ago
2004
IEEE
Simultaneous Multithreading (SMT) is emerging as an effective microarchitecture model to increase the utilization of resources in modern super-scalar processors. However, co-sched...
DSD
2009
IEEE
13 years 11 months ago
2009
IEEE
Feature sizes in VLSI circuits are steadily shrinking. This results in increasing susceptibility to soft errors, e.g. due to environmental radiation. Precautions against soft error...