72 search results - page 2 / 15 » The design of a low power asynchronous multiplier |
ISCAS
2005
IEEE
13 years 11 months ago
2005
IEEE
- This paper describes the design of a low power
DAC
2005
ACM
13 years 7 months ago
2005
ACM
This paper proposes a low power technique, called SBR (Sign Bit Reduction) which may reduce the switching activity in multipliers as well as data buses. Utilizing the multipliers ...
ISLPED
1996
ACM
13 years 9 months ago
1996
ACM
This paper presents an accurate switched-current multiplier, designed for 3.3V supply voltage, performing 0.625M multiplications per second with a maximum nonlinearity of 0.94%. Th...
APCCAS
2006
IEEE
13 years 11 months ago
2006
IEEE
— We present a design technique for implementing asynchronous ALUs with CMOS domino logic and delay insensitive dual rail four-phase logic. It ensures economy in silicon area and...
ISCAS
2008
IEEE
13 years 12 months ago
2008
IEEE
—A simple low-area and low-power clock frequency multiplier is proposed for Delay Locked Loop (DLL) based clock synthesizers. In this circuit, 2n voltage controlled delay lines (...