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» Thermal-aware Steiner routing for 3D stacked ICs
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DAC
2011
ACM
12 years 4 months ago
Thermal-aware cell and through-silicon-via co-placement for 3D ICs
Existing thermal-aware 3D placement methods assume that the temperature of 3D ICs can be optimized by properly distributing the power dissipations, and ignoring the heat conductiv...
Jason Cong, Guojie Luo, Yiyu Shi
DAC
2012
ACM
11 years 7 months ago
Exploiting die-to-die thermal coupling in 3D IC placement
In this paper, we propose two methods used in 3D IC placement that effectively exploit the die-to-die thermal coupling in the stack. First, TSVs are spread on each die to reduce t...
Krit Athikulwongse, Mohit Pathak, Sung Kyu Lim
ICCAD
2009
IEEE
136views Hardware» more  ICCAD 2009»
13 years 2 months ago
Multi-functional interconnect co-optimization for fast and reliable 3D stacked ICs
Heat removal and power delivery have become two major reliability concerns in 3D stacked IC technology. For thermal problem, two possible solutions exist: thermal-through-silicon-...
Young-Joon Lee, Rohan Goel, Sung Kyu Lim
DATE
2009
IEEE
161views Hardware» more  DATE 2009»
13 years 11 months ago
Co-design of signal, power, and thermal distribution networks for 3D ICs
— Heat removal and power delivery are two major reliability concerns in the 3D stacked IC technology. Liquid cooling based on micro-fluidic channels is proposed as a viable solu...
Young-Joon Lee, Yoon Jo Kim, Gang Huang, Muhannad ...
GLVLSI
2009
IEEE
262views VLSI» more  GLVLSI 2009»
13 years 2 months ago
Power distribution paths in 3-D ICS
Distributing power and ground to a vertically integrated system is a complex and difficult task. Interplane communication and power delivery are achieved by through silicon vias (...
Vasilis F. Pavlidis, Giovanni De Micheli