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» Throughput Analysis of Synchronous Data Flow Graphs
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ASPDAC
2011
ACM
227views Hardware» more  ASPDAC 2011»
12 years 9 months ago
Minimizing buffer requirements for throughput constrained parallel execution of synchronous dataflow graph
– This paper concerns throughput-constrained parallel execution of synchronous data flow graphs. This paper assumes static mapping and dynamic scheduling of nodes, which has seve...
Tae-ho Shin, Hyunok Oh, Soonhoi Ha
SAC
2010
ACM
13 years 10 months ago
An algorithm to generate the context-sensitive synchronized control flow graph
The verification of industrial systems specified with CSP often implies the analysis of many concurrent and synchronized components. The cost associated to these analyses is usu...
Marisa Llorens, Javier Oliver, Josep Silva, Salvad...
ARC
2010
Springer
167views Hardware» more  ARC 2010»
13 years 8 months ago
Systolic Algorithm Mapping for Coarse Grained Reconfigurable Array Architectures
Coarse Grained Reconfigurable Array (CGRA) architectures give high throughput and data reuse for regular algorithms while providing flexibility to execute multiple algorithms on th...
Kunjan Patel, Chris J. Bleakley
BMCBI
2010
144views more  BMCBI 2010»
13 years 10 days ago
Optimizing Transformations for Automated, High Throughput Analysis of Flow Cytometry Data
Background: In a high throughput setting, effective flow cytometry data analysis depends heavily on proper data preprocessing. While usual preprocessing steps of quality assessmen...
Greg Finak, Juan-Manuel Perez, Andrew Weng, Raphae...
DAC
1997
ACM
13 years 9 months ago
Data Memory Minimisation for Synchronous Data Flow Graphs Emulated on DSP-FPGA Targets
The paper presents an algorithm to determine the close-tosmallest possible data buffer sizes for arbitrary synchronous data flow (SDF) applications, such that we can guarantee the...
Marleen Adé, Rudy Lauwereins, J. A. Peperst...