28 search results - page 2 / 6 » Timing Driven Placement for Quasi Delay-Insensitive Circuits |
DAC
1995
ACM
13 years 8 months ago
1995
ACM
ICCAD
2001
IEEE
14 years 1 months ago
2001
IEEE
Retiming is a widely investigated technique for performance optimization. It performs powerful modifications on a circuit netlist. However, often it is not clear, whether the pred...
FPL
2004
Springer
13 years 10 months ago
2004
Springer
Traditional placement algorithms for FPGAs are normally carried out on a fixed clustering solution of a circuit. The impact of clustering on wirelength and delay of the placement s...
ICCAD
1995
IEEE
13 years 8 months ago
1995
IEEE
In a typical design
ow, the design may be altered slightly several times after the initial design cycle according to minor changes in the design speci cation either as a result o...
DAC
2006
ACM
14 years 5 months ago
2006
ACM
In this paper, we propose a new linear programming based timing driven placement framework for high performance designs. Our LP framework is mainly net-based, but it takes advanta...