28 search results - page 3 / 6 » Timing Driven Placement for Quasi Delay-Insensitive Circuits |
GLVLSI
2007
IEEE
13 years 11 months ago
2007
IEEE
We present new timing and congestion driven FPGA placement algorithms with minimal runtime overhead. By predicting the post-routing critical edges and estimating congestion accura...
GLVLSI
2000
IEEE
13 years 9 months ago
2000
IEEE
: We propose a novel evolutionary approach to the problem of timing-driven FPGA placement. The method used is evolutionary programming (EP) with incremental position encoded in the...
ICCAD
2004
IEEE
14 years 2 months ago
2004
IEEE
Traditional timing-driven placement considers only combinational delays and does not take into account the potential of subsequent sequential optimization steps. As a result, the ...
VLSI
2007
Springer
13 years 11 months ago
2007
Springer
— While physically driven synthesis techniques have proven to be an effective method to meet tight timing constraints required by a design, the incremental placement step during ...
ICCAD
2003
IEEE
14 years 2 months ago
2003
IEEE
This work studies the optimality and stability of timing-driven placement algorithms. The contributions of this work include two parts: 1) We develop an algorithm for generating s...