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» Timing Optimization for Multi-Source Nets: Characterization ...
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VLSID
1999
IEEE
93views VLSI» more  VLSID 1999»
13 years 9 months ago
Spec-Based Repeater Insertion and Wire Sizing for On-chip Interconnect
Recently Lillis, et al. presented an elegant dynamic programming approach to RC interconnect delay optimization through driver sizing, repeater insertion, and, wire sizing which e...
Noel Menezes, Chung-Ping Chen
NANONET
2009
Springer
200views Chemistry» more  NANONET 2009»
13 years 11 months ago
Repeater Insertion for Two-Terminal Nets in Three-Dimensional Integrated Circuits
A new approach for inserting repeaters in 3-D interconnects is proposed. The allocation of repeaters along an interplane interconnect is iteratively determined. The proposed approa...
Hu Xu, Vasilis F. Pavlidis, Giovanni De Micheli
DAC
1999
ACM
14 years 5 months ago
Noise-Aware Repeater Insertion and Wire-Sizing for On-Chip Interconnect Using Hierarchical Moment-Matching
Recently, several algorithms for interconnect optimization via repeater insertion and wire sizing have appeared based on the Elmore delay model. Using the Devgan noise metric [6] ...
Chung-Ping Chen, Noel Menezes