118 search results - page 2 / 24 » Timing constraint specification and synthesis in behavioral ... |
DATE
2003
IEEE
13 years 10 months ago
2003
IEEE
Embedded systems design requires the development of complex HW modules to cope with the most stringent timing constraints of the specifications. This implies the need to update an...
DAC
2006
ACM
14 years 6 months ago
2006
ACM
We address the problem of estimating controller delay from high-level specifications during behavioral synthesis. Typically, the critical path of a synthesised behavioral design g...
ASPDAC
2008
ACM
13 years 7 months ago
2008
ACM
This paper proposes a novel Behavioral Synthesis method that improves performance of synthesized circuits utilizing specialized functional units effectively. Specialized functional...
RSP
1999
IEEE
13 years 9 months ago
1999
IEEE
SDL is currently gaining interest as a system level specification language for HW/SW codesign. Automated synthesis of SDL in hardware so far had problems with its efficiency. The ...
VLSID
2005
IEEE
14 years 5 months ago
2005
IEEE
High level synthesis tools transform an algorithmic description to a register transfer language (RTL) description of the hardware. The algorithm behavior is typically described in...