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» Timing optimization by bit-level arithmetic transformations
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EURODAC
1995
IEEE
126views VHDL» more  EURODAC 1995»
13 years 8 months ago
Timing optimization by bit-level arithmetic transformations
This paper describes a method to optimize the performance of data paths. It is based on bit-level arithmetic transformations, and is especially suited to optimize large adder stru...
Luc Rijnders, Zohair Sahraoui, Paul Six, Hugo De M...
ICCD
2004
IEEE
100views Hardware» more  ICCD 2004»
14 years 1 months ago
Layout Driven Optimization of Datapath Circuits using Arithmetic Reasoning
This paper proposes a new formalism for layout-driven optimization of datapaths. It is based on preserving an arithmetic bit level representation of the arithmetic circuit portion...
Ingmar Neumann, Dominik Stoffel, Kolja Sulimma, Mi...
ASPDAC
2008
ACM
106views Hardware» more  ASPDAC 2008»
13 years 5 months ago
Verifying full-custom multipliers by Boolean equivalence checking and an arithmetic bit level proof
—In this paper we describe a practical methodology to formally verify highly optimized, industrial multipliers. We a multiplier description language which abstracts from low-leve...
Udo Krautz, Markus Wedler, Wolfgang Kunz, Kai Webe...
TPCD
1994
157views Hardware» more  TPCD 1994»
13 years 6 months ago
Non-Restoring Integer Square Root: A Case Study in Design by Principled Optimization
Theorem proving techniques are particularly well suited for reasoning about arithmetic above the bit level and for relating di erent f abstraction. In this paper we show how a non-...
John W. O'Leary, Miriam Leeser, Jason Hickey, Mark...
DAC
1998
ACM
13 years 9 months ago
Arithmetic Optimization Using Carry-Save-Adders
Carry-save-adderCSA is the most often used type of operation in implementing a fast computation of arithmetics of register-transfer level design in industry. This paper establis...
Taewhan Kim, William Jao, Steven W. K. Tjiang