77 search results - page 1 / 16 » Timing optimization by restructuring long combinatorial path... |
ICCAD
2007
IEEE
14 years 1 months ago
2007
IEEE
—We present an implementation of an algorithm for constructing provably fast circuits for a class of Boolean functions with input signals that have individual starting times. We ...
ICCAD
1999
IEEE
13 years 9 months ago
1999
IEEE
: In this paper, an algorithm for simultaneous logic restructuring and placement is presented. This algorithm first constructs a set of super-cells along the critical paths and the...
TCAD
2008
13 years 4 months ago
2008
The relatively poor scaling of interconnect in modern digital circuits necessitates a number of design optimizations, which must typically be iterated several times to meet the spe...
GLVLSI
2008
IEEE
13 years 11 months ago
2008
IEEE
Timing optimizations during logic synthesis has become a necessary step to achieve timing closure in VLSI designs. This often involves “shortening” all paths found in the circ...
EOR
2007
13 years 4 months ago
2007
This paper investigates, for the first time in the literature, the approximation of minmax (regret) versions of classical problems like shortest path, minimum spanning tree, and ...