51 search results - page 2 / 11 » Timing variation-aware high-level synthesis |
ISSS
1997
IEEE
13 years 9 months ago
1997
IEEE
This paper presents a novel source-level dynamic analysis methodology and tool for High-Level Synthesis (HLS). It not only for the first time enables HLS to offer source-level de...
ISQED
2007
IEEE
13 years 11 months ago
2007
IEEE
In high-level synthesis for FPGA designs, scheduling and chaining of operations for optimal performance remain challenging problems. In this paper, we present a balanced schedulin...
DATE
2002
IEEE
13 years 10 months ago
2002
IEEE
Optimizing power consumption at high-level is a critical step towards power-efficient digital system designs. This paper addresses the power management problem by scheduling a giv...
GLVLSI
2000
IEEE
13 years 10 months ago
2000
IEEE
In this paper we present a novel and fast estimation technique that produces tight latency lower bounds for Data Flow Graphs representing time critical segments of the application...
DAC
1994
ACM
13 years 9 months ago
1994
ACM
Abstract -- This paper describes a new memory estimation technique for DSP applications written in an applicative language. Since no concept of storage is present in an applicative...