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ISCAS
2005
IEEE
131views Hardware» more  ISCAS 2005»
13 years 10 months ago
Timing yield estimation using statistical static timing analysis
—As process variations become a significant problem in deep sub-micron technology, a shift from deterministic static timing analysis to statistical static timing analysis for hig...
Min Pan, Chris C. N. Chu, Hai Zhou
DAC
2004
ACM
14 years 5 months ago
Statistical timing analysis based on a timing yield model
Starting from a model of the within-die systematic variations using principal components analysis, a model is proposed for estimation of the parametric yield, and is then applied ...
Farid N. Najm, Noel Menezes
TVLSI
2008
105views more  TVLSI 2008»
13 years 4 months ago
Fast Estimation of Timing Yield Bounds for Process Variations
With aggressive scaling down of feature sizes in VLSI fabrication, process variation has become a critical issue in designs. We show that two necessary conditions for the "Max...
Ruiming Chen, Hai Zhou
ICCAD
2005
IEEE
176views Hardware» more  ICCAD 2005»
14 years 1 months ago
Statistical gate sizing for timing yield optimization
— Variability in the chip design process has been relatively increasing with technology scaling to smaller dimensions. Using worst case analysis for circuit optimization severely...
Debjit Sinha, Narendra V. Shenoy, Hai Zhou
TCAD
2008
98views more  TCAD 2008»
13 years 4 months ago
Early Analysis and Budgeting of Margins and Corners Using Two-Sided Analytical Yield Models
Manufacturing process variations lead to variability in circuit delay and, if not accounted for, can cause excessive timing yield loss. The familiar traditional approaches to timin...
Khaled R. Heloue, Farid N. Najm