120 search results - page 2 / 24 » Timing-driven placement for FPGAs |
ICCD
1997
IEEE
13 years 9 months ago
1997
IEEE
Simulated annealing based standard cell placement for VLSI designs has long been acknowledged as a compute-intensive process. All previous work in parallel simulated annealing bas...
ASPDAC
2007
ACM
13 years 9 months ago
2007
ACM
TCAD
2008
13 years 5 months ago
2008
Physical synthesis tools are responsible for achieving timing closure. Starting with 130nm designs, multiple cycles are required to cross the chip, making latch placement critical...
ISPD
2003
ACM
13 years 10 months ago
2003
ACM
This paper presents a new timing driven force directed placement algorithm that meets physical net length constraints as well as constraints on specific pin sets. It is the first ...
DAC
2006
ACM
14 years 6 months ago
2006
ACM
In this paper, we propose a new linear programming based timing driven placement framework for high performance designs. Our LP framework is mainly net-based, but it takes advanta...