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ASPDAC
2005
ACM
146views Hardware» more  ASPDAC 2005»
13 years 7 months ago
High-level synthesis for DSP applications using heterogeneous functional units
Abstract— This paper addresses high level synthesis for realtime digital signal processing (DSP) architectures using heterogeneous functional units (FUs). For such special purpos...
Zili Shao, Qingfeng Zhuge, Chun Xue, Bin Xiao, Edw...
ISLPED
2009
ACM
125views Hardware» more  ISLPED 2009»
14 years 2 days ago
Behavior-level observability don't-cares and application to low-power behavioral synthesis
Many techniques for power management employed in advanced RTL synthesis tools rely explicitly or implicitly on observability don’t-care (ODC) conditions. In this paper we presen...
Jason Cong, Bin Liu, Zhiru Zhang
ASPDAC
2009
ACM
152views Hardware» more  ASPDAC 2009»
14 years 2 days ago
A novel Toffoli network synthesis algorithm for reversible logic
—Reversible logic studies have promising potential on energy lossless circuit design, quantum computation, nanotechnology, etc. Reversible logic features a one-to-one input outpu...
Yexin Zheng, Chao Huang
IPPS
1997
IEEE
13 years 9 months ago
A Comparison of Parallel Approaches for Algebraic Factorization in Logic Synthesis
Algebraic factorization is an extremely important part of any logic synthesis system but is computationally expensive. Hence it is important to look at parallel processing to spee...
Sumit Roy, Prithviraj Banerjee
ICCAD
2001
IEEE
97views Hardware» more  ICCAD 2001»
14 years 2 months ago
Addressing the Timing Closure Problem by Integrating Logic Optimization and Placement
Timing closure problems occur when timing estimates computed during logic synthesis do not match with timing estimates computed from the layout of the circuit. In such a situation...
Wilsin Gosti, Sunil P. Khatri, Alberto L. Sangiova...