48 search results - page 2 / 10 » Toward Formalizing a Validation Methodology Using Simulation... |
DATE
2006
IEEE
13 years 11 months ago
2006
IEEE
—In this paper we describe a methodology to measure exactly the quality of fault-tolerant designs by combining faultinjection in high level design (HLD) descriptions with a forma...
CODES
2008
IEEE
13 years 7 months ago
2008
IEEE
Functional validation is a major bottleneck in microprocessor design methodology. Simulation is the widely used method for functional validation using billions of random and biase...
TC
1998
13 years 5 months ago
1998
ion Techniques for Validation Coverage Analysis and Test Generation Dinos Moundanos, Jacob A. Abraham, Fellow, IEEE, and Yatin V. Hoskote —The enormous state spaces which must be...
DT
2000
13 years 5 months ago
2000
f abstraction as applicable to break the problem's complexity, and innovating better techniques to address complexity of new microarchitectural features. Validation techniques...
IFIP
2001
Springer
13 years 9 months ago
2001
Springer
— Semi-formal verification based on symbolic simulation offers a good compromise between formal model checking and numerical simulation. The generation of functional test vector...