110 search results - page 2 / 22 » Two VLSI Design Advances in Arithmetic Coding |
TCSV
2002
13 years 4 months ago
2002
This paper presents an efficient VLSI architecture design of MPEG-4 shape coding, which is the key technology for supporting the content-based functionality of the MPEG-4 Video sta...
DFT
2004
IEEE
13 years 8 months ago
2004
IEEE
This paper addresses the problem of test response compaction. In order to maximize compaction ratio, a single-output encoder based on check matrix of a (n, n1, m, 3) convolutional...
GLVLSI
2003
IEEE
13 years 10 months ago
2003
IEEE
Clock-delayed (CD) domino is a dynamic logic family developed to provide both inverting and non-inverting logic on single-rail gates. It is self-timed and can be easily pipelined ...
VLSI
2007
Springer
13 years 11 months ago
2007
Springer
Abstract— In this paper, a low-power deblocking filter architecture for H.264/AVC is proposed. A hybrid filtering order has been adopted to boost the speed of the deblocking ...
GLVLSI
1998
IEEE
13 years 9 months ago
1998
IEEE
Interval arithmetic provides an e cient method for monitoring and controlling errors in numerical calculations. However, existing software packages for interval arithmetic are oft...