3 search results - page 1 / 1 » Two-Dimensional Test Data Compression for Scan-Based Determi... |
ET
2002
13 years 4 months ago
2002
In this paper a novel architecture for scan-based mixed mode BIST is presented. To reduce the storage requirements for the deterministic patterns it relies on a two-dimensional co...
ITC
1996
IEEE
13 years 9 months ago
1996
IEEE
This paper presents a low-overhead scheme for built-in self-test of circuits with scan. Complete (100%) fault coverage is obtained without modifying the function logic and without...
DAC
2003
ACM
13 years 10 months ago
2003
ACM
We present a novel method to efficiently generate, compress and apply test patterns in a logic BIST architecture. Patterns are generated by a modified automatic test pattern gener...