11 search results - page 1 / 3 » Type-matching clock tree for zero skew clock gating |
DAC
2008
ACM
14 years 5 months ago
2008
ACM
Clock skew minimization is always very important in the clock tree synthesis. Due to clock gating, the clock tree may include different types of logic gates, e.g., AND gates, OR g...
ISPD
2010
ACM
13 years 11 months ago
2010
ACM
NBTI (Negative Bias Temperature Instability) has emerged as the dominant failure mechanism for PMOS in nanometer IC designs. However, its impact on one of the most important compo...
ISPD
2000
ACM
13 years 9 months ago
2000
ACM
In this paper, we propose a new clock tree synthesis method for semi-synchronous circuits. A clock tree obtained by the proposed method is a multi-level multi-way clock tree such ...
DATE
2009
IEEE
13 years 11 months ago
2009
IEEE
NBTI (Negative Bias Temperature Instability) has emerged as the dominant PMOS device failure mechanism for sub100nm VLSI designs. There is little research to quantify its impact o...
ICCAD
1999
IEEE
13 years 8 months ago
1999
IEEE
We introduce the associative skew clock routing problem, which seeks a clock routing tree such that zero skew is preserved only within identified groups of sinks. The associative ...