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» Universal Switch Blocks for Three-Dimensional FPGA Design
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DAC
2006
ACM
14 years 6 months ago
Synthesis of high-performance packet processing pipelines
Packet editing is a fundamental building block of data communication systems such as switches and routers. Circuits that implement this function are critical and define the featur...
Cristian Soviani, Ilija Hadzic, Stephen A. Edwards
FPL
2009
Springer
145views Hardware» more  FPL 2009»
13 years 10 months ago
Run-time Partial Reconfiguration speed investigation and architectural design space exploration
Run-time Partial Reconfiguration (PR) speed is significant in applications especially when fast IP core switching is required. In this paper, we propose to use Direct Memory Acce...
Ming Liu, Wolfgang Kuehn, Zhonghai Lu, Axel Jantsc...
DAC
2005
ACM
14 years 6 months ago
Device and architecture co-optimization for FPGA power reduction
Device optimization considering supply voltage Vdd and threshold voltage Vt tuning does not increase chip area but has a great impact on power and performance in the nanometer tec...
Lerong Cheng, Phoebe Wong, Fei Li, Yan Lin, Lei He
VLSID
2007
IEEE
210views VLSI» more  VLSID 2007»
14 years 6 months ago
Dynamically Optimizing FPGA Applications by Monitoring Temperature and Workloads
In the past, Field Programmable Gate Array (FPGA) circuits only contained a limited amount of logic and operated at a low frequency. Few applications running on FPGAs consumed exc...
Phillip H. Jones, Young H. Cho, John W. Lockwood
FPGA
2009
ACM
183views FPGA» more  FPGA 2009»
14 years 13 days ago
A comparison of via-programmable gate array logic cell circuits
Via-programmable gate arrays (VPGAs) offer a middle ground between application specific integrated circuits and field programmable gate arrays in terms of flexibility, manufac...
Thomas C. P. Chau, Philip Heng Wai Leong, Sam M. H...