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» Universal Test Sets for Reversible Circuits
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ATS
2005
IEEE
164views Hardware» more  ATS 2005»
13 years 7 months ago
A Family of Logical Fault Models for Reversible Circuits
Reversibility is of interest in achieving extremely low power dissipation; it is also an inherent design requirement of quantum computation. Logical fault models for conventional ...
Ilia Polian, Thomas Fiehn, Bernd Becker, John P. H...
VLSID
2003
IEEE
96views VLSI» more  VLSID 2003»
14 years 5 months ago
Design Of A Universal BIST (UBIST) Structure
This paper introduces a Built-In Self Test (BIST) structure referred to as Universal BIST (UBIST). The Test Pattern Generator (TPG) of the proposed UBIST is designed to generate an...
Sukanta Das, Niloy Ganguly, Biplab K. Sikdar, Pari...
ICCAD
1995
IEEE
180views Hardware» more  ICCAD 1995»
13 years 8 months ago
Design based analog testing by Characteristic Observation Inference
In this paper, a new approach to analog test design based on the circuit design process, called Characteristic Observation Inference (COI), is presented. In many situations, it is...
Walter M. Lindermeir, Helmut E. Graeb, Kurt Antrei...
EURODAC
1995
IEEE
164views VHDL» more  EURODAC 1995»
13 years 8 months ago
Bottleneck removal algorithm for dynamic compaction and test cycles reduction
: We present a new, dynamic algorithm for test sequence compaction and test cycle reduction for combinationaland sequential circuits. Several dynamic algorithms for compaction in c...
Srimat T. Chakradhar, Anand Raghunathan
ASPDAC
2006
ACM
144views Hardware» more  ASPDAC 2006»
13 years 11 months ago
Compaction of pass/fail-based diagnostic test vectors for combinational and sequential circuits
Abstract— Substantial attention is being paid to the fault diagnosis problem in recent test literature. Yet, the compaction of test vectors for fault diagnosis is little explored...
Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahas...