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EUROPAR
2010
Springer
13 years 6 months ago
Thread Owned Block Cache: Managing Latency in Many-Core Architecture
Abstract. Shared last level cache is crucial to performance. However, multithread program model incurs serious contention in shared cache. In this paper, to reduce average cache ac...
Fenglong Song, Zhiyong Liu, Dongrui Fan, Hao Zhang...
PPOPP
2009
ACM
14 years 6 months ago
A compiler-directed data prefetching scheme for chip multiprocessors
Data prefetching has been widely used in the past as a technique for hiding memory access latencies. However, data prefetching in multi-threaded applications running on chip multi...
Dhruva Chakrabarti, Mahmut T. Kandemir, Mustafa Ka...
CGO
2006
IEEE
13 years 11 months ago
Thread-Shared Software Code Caches
Software code caches are increasingly being used to amortize the runtime overhead of dynamic optimizers, simulators, emulators, dynamic translators, dynamic compilers, and other t...
Derek Bruening, Vladimir Kiriansky, Timothy Garnet...
HPCA
2011
IEEE
12 years 9 months ago
MOPED: Orchestrating interprocess message data on CMPs
Future CMPs will combine many simple cores with deep cache hierarchies. With more cores, cache resources per core are fewer, and must be shared carefully to avoid poor utilization...
Junli Gu, Steven S. Lumetta, Rakesh Kumar, Yihe Su...
HPCA
2009
IEEE
14 years 6 months ago
Dynamic hardware-assisted software-controlled page placement to manage capacity allocation and sharing within large caches
In future multi-cores, large amounts of delay and power will be spent accessing data in large L2/L3 caches. It has been recently shown that OS-based page coloring allows a non-uni...
Manu Awasthi, Kshitij Sudan, Rajeev Balasubramonia...