218 search results - page 1 / 44 » Using BIST Control for Pattern Generation |
ITC
1997
IEEE
13 years 10 months ago
1997
IEEE
A deterministic BIST scheme is presented which requires less hardware overhead than pseudo-random BIST but obtains better or even complete fault coverage at the same time. It take...
ASPDAC
2001
ACM
13 years 9 months ago
2001
ACM
Abstract--We present a processor-programmable built-in selftest (BIST) scheme suitable for embedded memory testing in the system-on-a-chip (SOC) environment. The proposed BIST circ...
ITC
1999
IEEE
13 years 10 months ago
1999
IEEE
This paper discusses practical issues involved in applying logic built-in self-test (BIST) to four large industrial designs. These multi-clock designs, ranging in size from 200K t...
VLSID
2001
IEEE
14 years 6 months ago
2001
IEEE
In this paper, we propose a new transparent built-in self-test ( TBIST ) method to test multiple embedded memory arrays with various sizes in parallel. First, a new transparent tes...
VTS
1998
IEEE
13 years 10 months ago
1998
IEEE
This paper presents a BIST architecture for Finite State Machines that exploits Cellular Automata (CA) as pattern generators and signature analyzers. The main advantage of the pro...