30 search results - page 2 / 6 » Variability in nanometer CMOS: Impact, analysis, and minimiz... |
DAC
2006
ACM
13 years 11 months ago
2006
ACM
VLSI engineers have traditionally used a variety of CAD analysis tools (e.g. SPICE) to deal with variability. As we go into deep sub micron issues, the analysis is becoming harder...
DAC
2006
ACM
13 years 11 months ago
2006
ACM
Negative bias temperature instability (NBTI) has become the dominant reliability concern for nanoscale PMOS transistors. In this paper, a predictive model is developed for the deg...
DATE
2009
IEEE
14 years 2 hour ago
2009
IEEE
— Lithographic variability and its impact on printability is a major concern in today’s semiconductor manufacturing process. To address sub-wavelength printability, a number of...
DATE
2005
IEEE
13 years 11 months ago
2005
IEEE
In nanometer scaled CMOS devices significant increase in the subthreshold, the gate and the reverse biased junction band-toband-tunneling (BTBT) leakage, results in the large incr...
CODES
2006
IEEE
13 years 11 months ago
2006
IEEE
Process variability has a detrimental impact on the performance of memories and other system components, which can lead to parametric yield loss at the system level due to timing ...