5 search results - page 1 / 1 » Variation tolerant buffered clock network synthesis with cro... |
ISPD
2006
ACM
13 years 11 months ago
2006
ACM
ISQED
2007
IEEE
13 years 11 months ago
2007
IEEE
Clock distribution is one of the key limiting factors in any high speed, sub-100nm VLSI design. Unwanted clock skews, caused by variation effects like manufacturing variations, po...
TVLSI
2010
13 years 3 hour ago
2010
Clock network is a vulnerable victim of variations as well as a main power consumer in many integrated circuits. Recently, link-based non-tree clock network attracts people's...
TCAD
2010
13 years 1 days ago
2010
Clock mesh networks are well known for their variation tolerance. But their usage is limited to high-end designs due to the significantly high resource requirements compared to clo...
ENTCS
2008
13 years 5 months ago
2008
This paper reports on the design of a test chip built to test a) a new latency insensitive network fabric protocol and circuits, b) a new synchronizer design, and c) how efficient...