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» Variation-aware resource sharing and binding in behavioral s...
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ASPDAC
2007
ACM
144views Hardware» more  ASPDAC 2007»
13 years 9 months ago
Control-Flow Aware Communication and Conflict Analysis of Parallel Processes
In this paper, we present an approach for control-flow aware communication and conflict analysis of systems of parallel communicating processes. This approach allows to determine ...
Axel Siebenborn, Alexander Viehl, Oliver Bringmann...
ICCAD
1995
IEEE
135views Hardware» more  ICCAD 1995»
13 years 9 months ago
An iterative improvement algorithm for low power data path synthesis
We address the problem of minimizing power consumption in behavioral synthesis of data-dominated circuits. The complex nature of power as a cost function implies that the effects ...
Anand Raghunathan, Niraj K. Jha
VLSID
2009
IEEE
155views VLSI» more  VLSID 2009»
14 years 6 months ago
Unified Challenges in Nano-CMOS High-Level Synthesis
: The challenges in nano-CMOS circuit design include the following: variability, leakage, power, thermals, reliability, and yield. This talk will focus on interdependent considerat...
Saraju P. Mohanty
ICCAD
2006
IEEE
131views Hardware» more  ICCAD 2006»
14 years 2 months ago
High-level synthesis challenges and solutions for a dynamically reconfigurable processor
A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone...
Takao Toi, Noritsugu Nakamura, Yoshinosuke Kato, T...
DSD
2010
IEEE
137views Hardware» more  DSD 2010»
13 years 3 months ago
A C-to-RTL Flow as an Energy Efficient Alternative to Embedded Processors in Digital Systems
We present a high-level synthesis flow for mapping an algorithm description (in C) to a provably equivalent registertransfer level (RTL) description of hardware. This flow uses an ...
Sameer D. Sahasrabuddhe, Sreenivas Subramanian, Ku...