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FPL
2010
Springer
104views Hardware» more  FPL 2010»
13 years 2 months ago
Multiplicative Square Root Algorithms for FPGAs
Abstract--Most current square root implementations for FPGAs use a digit recurrence algorithm which is well suited to their LUT structure. However, recent computing-oriented FPGAs ...
Florent de Dinechin, Mioara Joldes, Bogdan Pasca, ...
ASAP
2008
IEEE
161views Hardware» more  ASAP 2008»
13 years 6 months ago
Configurable and scalable high throughput turbo decoder architecture for multiple 4G wireless standards
In this paper, we propose a novel multi-code turbo decoder architecture for 4G wireless systems. To support various 4G standards, a configurable multi-mode MAP (maximum a posterio...
Yang Sun, Yuming Zhu, Manish Goel, Joseph R. Caval...
SIGCOMM
1997
ACM
13 years 9 months ago
Scalable High Speed IP Routing Lookups
Internet address lookup is a challenging problem because of increasing routing table sizes, increased traffic, higher speed links, and the migration to 128 bit IPv6 addresses. IP...
Marcel Waldvogel, George Varghese, Jonathan S. Tur...