9 search results - page 2 / 2 » Wave-pipelined on-chip global interconnect |
ASAP
2007
IEEE
13 years 7 months ago
2007
IEEE
Interconnect validation is an important early step toward global SoC (System-On-Chip) validation. Fast performances evaluation and design space exploration for NoCs (Networks-On-C...
DAC
2001
ACM
14 years 6 months ago
2001
ACM
Milenko Drinic UCLA Computer Science Dep. 4732 Boelter Hall Los Angeles, CA 90095-1596 milenko@cs.ucla.edu Darko Kirovski Microsoft Research One Microsoft Way Redmond, WA 98052 da...
ICCAD
2000
IEEE
13 years 9 months ago
2000
IEEE
Abstract— Deep submicron technology scaling has two major ramifications on the design process. First, reduced feature size significantly increases wire delay, thus resulting in...
SLIP
2009
ACM
13 years 12 months ago
2009
ACM
Different interconnection structures have been proposed to solve the performance limitation caused by scaling of on-chip global wires. In this paper, we give an overview of curre...