An accurate model for pre-placement wire length estimation can be a useful tool during the physical design of integrated circuits. In this paper, an a priori wire length estimatio...
We investigate coding techniques to reduce the energy consumed by on-chip buses in a microprocessor. We explore several simple coding schemes and simulate them using a modified Si...
Victor Wen, Mark Whitney, Yatish Patel, John Kubia...
Since across-chip interconnect delays can exceed a clock cycle in nanometer technologies, it has become essential in high performance designs to add flip-flops on wires with multi...
Vidyasagar Nookala, Ying Chen, David J. Lilja, Sac...
In the past, a priori interconnect prediction, based on Rent’s rule, has been applied mainly for technology evaluation and roadmap applications. These applications do not requir...
We address the classic wire-length estimation problem and propose a new statistical wire-length estimation approach that captures the probability distribution function of net leng...
Jennifer L. Wong, Azadeh Davoodi, Vishal Khandelwa...