10 search results - page 1 / 2 » Wirelength reduction by using diagonal wire |
GLVLSI
2003
IEEE
13 years 10 months ago
2003
IEEE
ISPD
2007
ACM
13 years 6 months ago
2007
ACM
In this paper, we derive the X-half-perimeter wirelength (XHPWL) model for X-architecture placement and explore the effects of three different wire models on X-architecture plac...
DAC
2005
ACM
14 years 5 months ago
2005
ACM
As technology advances into the nanometer territory, the interconnect delay has become a first-order effect on chip performance. To handle this effect, the X-architecture has been...
ASPDAC
2005
ACM
13 years 10 months ago
2005
ACM
— The recent popularity of 3D IC technology stems from its enhanced performance capabilities and reduced wirelength. However, wire congestion and thermal issues are exacerbated d...
ISCAS
2006
IEEE
13 years 10 months ago
2006
IEEE
— The X-architecture is a new integrated-circuit wiring technique in the physical design. Compared with the currently used M-architecture, which uses either horizontal or vertica...