19 search results - page 1 / 4 » Yield Estimation of VLSI Circuits with Downscaled Layouts |
DFT
1999
IEEE
13 years 9 months ago
1999
IEEE
This paper describes the yield estimation approach to layout scaling of submicron VLSI circuits. The presented method makes it feasible to find scaling factor of the IC design whi...
DFT
2004
IEEE
13 years 8 months ago
2004
IEEE
We present a model for computing the probability of a parametric failure due to a spot defect. The analysis is based on electromigration in conductors under unidirectional current...
VLSID
2002
IEEE
14 years 5 months ago
2002
IEEE
This paper presents a new method to compute the probability distribution of the delay of a combinational circuit and uses it obtain an estimate of the yield of the process that ma...
CDES
2006
13 years 6 months ago
2006
The ability to improve the yield of integrated circuits through layout modification has been recognized and several techniques for yield enhanced routing and compaction have been ...
ISPD
2000
ACM
13 years 9 months ago
2000
ACM
We address the problem of computing critical area for missing material defects in a circuit layout. The extraction of critical area is the main computational problem in VLSI yield...