35 search results - page 2 / 7 » Yield modelling and Yield Enhancement for FPGAs using Fault ... |
GLVLSI
2006
IEEE
13 years 11 months ago
2006
IEEE
This paper presents a systematic design methodology for yield enhancement of asynchronous logic circuits using 3-D (3-Dimensional) integration technology. In this design, the targ...
DFT
1999
IEEE
13 years 9 months ago
1999
IEEE
A programmable single-chip multiprocessor system for video coding has been developed. The system is implemented in a high-performance 0.25 m logic/embedded DRAM process. It integr...
FPGA
2007
ACM
13 years 11 months ago
2007
ACM
Variations in the semiconductor fabrication process results in variability in parameters between transistors on the same die, a problem exacerbated by lithographic scaling. The re...
DFT
1997
IEEE
13 years 9 months ago
1997
IEEE
Recent increases in the density and size of memory ICs made it ne cessary to search for new defect tolerance techniques since the traditional methods are no longer e ective enough...
TC
1998
13 years 4 months ago
1998
—The very high levels of integration and submicron device sizes used in current and emerging VLSI technologies for FPGAs lead to higher occurrences of defects and operational fau...