Sciweavers

53 search results - page 10 / 11
» isca 2009
Sort
View
GLVLSI
2009
IEEE
167views VLSI» more  GLVLSI 2009»
13 years 12 months ago
Dual-threshold pass-transistor logic design
This paper introduces pass-transistor logic design with dualthreshold voltages. A set of single-rail, fully restored, passtransistor gates are presented. Logic transistors are imp...
Lara D. Oliver, Krishnendu Chakrabarty, Hisham Z. ...
ASPDAC
2009
ACM
262views Hardware» more  ASPDAC 2009»
13 years 11 months ago
Fault modeling and testing of retention flip-flops in low power designs
Low power circuits have become a necessary part in modern designs. Retention flip-flop is one of the most important components in low power designs. Conventional test methodologie...
Bing-Chuan Bai, Augusli Kifli, Chien-Mo James Li, ...
GLVLSI
2009
IEEE
128views VLSI» more  GLVLSI 2009»
13 years 9 months ago
Impact of lithography-friendly circuit layout
Current lithography techniques use a light wavelength of 193nm to print sub-65nm features. This introduces process variations which cause mismatches between desired and actual waf...
Pratik J. Shah, Jiang Hu
ICCAD
2009
IEEE
96views Hardware» more  ICCAD 2009»
13 years 3 months ago
PSTA-based branch and bound approach to the silicon speedpath isolation problem
The lack of good "correlation" between pre-silicon simulated delays and measured delays on silicon (silicon data) has spurred efforts on so-called silicon debug. The ide...
Sari Onaissi, Khaled R. Heloue, Farid N. Najm
DAC
2009
ACM
14 years 1 days ago
Clock skew optimization via wiresizing for timing sign-off covering all process corners
Manufacturing process variability impacts the performance of synchronous logic circuits by means of its effect on both clock network and functional block delays. Typically, varia...
Sari Onaissi, Khaled R. Heloue, Farid N. Najm