High defect coverage requires good coverage of different fault types. In this paper, we present a comprehensive test vector generation technique for BIST, called Random Single Inp...
We study the combination of face verification algorithms in order to improve the verification performance. Although the different face experts that we consider provide their outpu...
Fault diagnosis is to predict the potential fault sites in a logic IC. In this paper, we particularly address the problem of diagnosing faults that exhibit the so-called Byzantine...
Parallel test application helps reduce the otherwise considerable test times in SOCs; yet its applicability is limited by average and peak power considerations. The typical test v...
Ozgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailog...
The ever increasing trend to reduce DPM levels of memories requires tests with very high fault coverages. The very important class of dynamic fault, therefore cannot be ignored an...