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VTS
2002
IEEE
108views Hardware» more  VTS 2002»
13 years 9 months ago
On Using Efficient Test Sequences for BIST
High defect coverage requires good coverage of different fault types. In this paper, we present a comprehensive test vector generation technique for BIST, called Random Single Inp...
René David, Patrick Girard, Christian Landr...
ICPR
2002
IEEE
14 years 5 months ago
Combining Face Verification Experts
We study the combination of face verification algorithms in order to improve the verification performance. Although the different face experts that we consider provide their outpu...
Jacek Czyz, Josef Kittler, Luc Vandendorpe
VTS
2002
IEEE
101views Hardware» more  VTS 2002»
13 years 9 months ago
Speeding Up The Byzantine Fault Diagnosis Using Symbolic Simulation
Fault diagnosis is to predict the potential fault sites in a logic IC. In this paper, we particularly address the problem of diagnosing faults that exhibit the so-called Byzantine...
Shi-Yu Huang
VTS
2002
IEEE
138views Hardware» more  VTS 2002»
13 years 9 months ago
Test Power Reduction through Minimization of Scan Chain Transitions
Parallel test application helps reduce the otherwise considerable test times in SOCs; yet its applicability is limited by average and peak power considerations. The typical test v...
Ozgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailog...
VTS
2002
IEEE
113views Hardware» more  VTS 2002»
13 years 9 months ago
Testing Static and Dynamic Faults in Random Access Memories
The ever increasing trend to reduce DPM levels of memories requires tests with very high fault coverages. The very important class of dynamic fault, therefore cannot be ignored an...
Said Hamdioui, Zaid Al-Ars, A. J. van de Goor