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2002
IEEE

Test Power Reduction through Minimization of Scan Chain Transitions

10 years 3 months ago
Test Power Reduction through Minimization of Scan Chain Transitions
Parallel test application helps reduce the otherwise considerable test times in SOCs; yet its applicability is limited by average and peak power considerations. The typical test vector loading techniques result in frequent transitions in the scan chain, which in turn reflect into significant levels of circuit switching unnecessarily. Judicious utilization of logic in the scan chain can help reduce transitions while loading the test vector needed. No performance degradation ensues as scan chain modifications have no impact on functional execution. A computationally efficient scheme is proposed to identify the location and type of the logic to be inserted. The experimental results confirm the significant reductions in test power possible under the proposed scheme.
Ozgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailog
Added 16 Jul 2010
Updated 16 Jul 2010
Type Conference
Year 2002
Where VTS
Authors Ozgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailoglu
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