Sciweavers

Share
VTS
2002
IEEE

On Using Efficient Test Sequences for BIST

10 years 3 months ago
On Using Efficient Test Sequences for BIST
High defect coverage requires good coverage of different fault types. In this paper, we present a comprehensive test vector generation technique for BIST, called Random Single Input Change (RSIC) generation, that can be used to generate tests for many arbitrary misbehaviors that can occur in digital systems, thus providing a single on-chip test generation solution.
René David, Patrick Girard, Christian Landr
Added 16 Jul 2010
Updated 16 Jul 2010
Type Conference
Year 2002
Where VTS
Authors René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
Comments (0)
books