On Using Efficient Test Sequences for BIST

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High defect coverage requires good coverage of different fault types. In this paper, we present a comprehensive test vector generation technique for BIST, called Random Single Input Change (RSIC) generation, that can be used to generate tests for many arbitrary misbehaviors that can occur in digital systems, thus providing a single on-chip test generation solution.

René David, Patrick Girard, Christian Landr

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On-chip Test Generation | Random Single Input | Test Vector Generation | VLSI | VTS 2002 |

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Added	16 Jul 2010
Updated	16 Jul 2010
Type	Conference
Year	2002
Where	VTS
Authors	René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel

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On Using Efficient Test Sequences for BIST

On-chip Test Generation | Random Single Input | Test Vector Generation | VLSI | VTS 2002 |

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