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DFT
2004
IEEE
78views VLSI» more  DFT 2004»
13 years 8 months ago
Reliability Modeling and Assurance of Clockless Wave Pipeline
This paper presents theoretical yet practical methodologies to model, assure and optimize the Reliability of Clockless Wave Pipeline. Clockless wave pipeline is a cutting-edge and...
T. Feng, Nohpill Park, Yong-Bin Kim, Fabrizio Lomb...
DFT
2004
IEEE
95views VLSI» more  DFT 2004»
13 years 8 months ago
Mixed Loopback BiST for RF Digital Transceivers
In this paper we analyze the performance of a mixed built-in-self-test (BiST) for RF IC digital transceivers, where a baseband processor can be used both as a test pattern generat...
Jerzy Dabrowski, Javier Gonzalez Bayon
DFT
2004
IEEE
93views VLSI» more  DFT 2004»
13 years 8 months ago
First Level Hold: A Novel Low-Overhead Delay Fault Testing Technique
This paper presents a novel delay fault testing technique, which can be used as an alternative to the enhanced scan based delay fault testing, with significantly less design overh...
Swarup Bhunia, Hamid Mahmoodi-Meimand, Arijit Rayc...
DFT
2004
IEEE
102views VLSI» more  DFT 2004»
13 years 8 months ago
Exploiting an I-IP for In-Field SOC Test
Paolo Bernardi, Maurizio Rebaudengo, Matteo Sonza ...
DFT
2004
IEEE
92views VLSI» more  DFT 2004»
13 years 8 months ago
Reliability and Yield: A Joint Defect-Oriented Approach
We present a model for computing the probability of a parametric failure due to a spot defect. The analysis is based on electromigration in conductors under unidirectional current...
Roman Barsky, Israel A. Wagner
DFT
2004
IEEE
174views VLSI» more  DFT 2004»
13 years 8 months ago
Defect Avoidance in a 3-D Heterogeneous Sensor
A 3D Heterogeneous Sensor using a stacked chip is investigated. Optical Active Pixel Sensor and IR Bolometer detectors are combined to create a multispectral pixel for aligned col...
Glenn H. Chapman, Vijay K. Jain, Shekhar Bhansali
GLVLSI
2009
IEEE
142views VLSI» more  GLVLSI 2009»
13 years 8 months ago
Design tools for emerging technologies
The rapidly expanding diversity of technology available at the nanoscale is disrupting the existing transistorcentric microelectronics design paradigm, resulting in nearly decade-l...
Jacob White
GLVLSI
2009
IEEE
128views VLSI» more  GLVLSI 2009»
13 years 8 months ago
Impact of lithography-friendly circuit layout
Current lithography techniques use a light wavelength of 193nm to print sub-65nm features. This introduces process variations which cause mismatches between desired and actual waf...
Pratik J. Shah, Jiang Hu
GLVLSI
2009
IEEE
143views VLSI» more  GLVLSI 2009»
13 years 8 months ago
Unified P4 (power-performance-process-parasitic) fast optimization of a Nano-CMOS VCO
In this paper, we present the design of a P4 (Power-PerformanceProcess-Parasitic) aware voltage controlled oscillator (VCO) at nanoCMOS technologies. Through simulations, we have ...
Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos
GLVLSI
2009
IEEE
158views VLSI» more  GLVLSI 2009»
13 years 8 months ago
Exploration of memory hierarchy configurations for efficient garbage collection on high-performance embedded systems
Modern embedded devices (e.g., PDAs, mobile phones) are now incorporating Java as a very popular implementation language in their designs. These new embedded systems include multi...
José Manuel Velasco, David Atienza, Katzali...