Sciweavers

IPPS
2007
IEEE
14 years 3 months ago
Optimizing the Fast Fourier Transform on a Multi-core Architecture
The rapid revolution in microprocessor chip architecture due to multicore technology is presenting unprecedented challenges to the application developers as well as system softwar...
Long Chen, Ziang Hu, Junmin Lin, Guang R. Gao
IEEEARES
2007
IEEE
14 years 3 months ago
Security Requirements for a Semantic Service-oriented Architecture
Service-oriented architectures (SOAs) are a commonly used paradigm for IT infrastructures in various fields. Due to their flexibility and the easy accessibility of their underly...
Stefan Durbeck, Rolf Schillinger, Jan Kolter
ICDE
2007
IEEE
166views Database» more  ICDE 2007»
14 years 3 months ago
Enforcing Context-Sensitive Policies in Collaborative Business Environments
As enterprises seek to engage in increasingly rich and agile forms of collaboration, they are turning towards service-oriented architectures that enable them to selectively expose...
Alberto Sardinha, Jinghai Rao, Norman M. Sadeh
ICCCN
2007
IEEE
14 years 3 months ago
Context Awareness through Cross-Layer Network Architecture
—Layered architectures are not sufficiently flexible to cope with the dynamics of wireless-dominated next generation communications. Cross-layer approaches may provide a better s...
Mohammad Abdur Razzaque, Simon Dobson, Paddy Nixon
GLVLSI
2007
IEEE
115views VLSI» more  GLVLSI 2007»
14 years 3 months ago
Novel architectures for efficient (m, n) parallel counters
Parallel counters are key elements in many arithmetic circuits, especially fast multipliers. In this paper, novel architectures and designs for high speed, low power (3, 2), (7, 3...
Sreehari Veeramachaneni, Lingamneni Avinash, Kirth...
GLOBECOM
2007
IEEE
14 years 3 months ago
OBIG: the Architecture of an Output Buffered Switch with Input Groups for Large Switches
—Large, fast switches require novel approaches to architecture and scheduling. In this paper, we propose the Output Buffered Switch with Input Groups (OBIG). We present simulatio...
Wladek Olesinski, Hans Eberle, Nils Gura
ECBS
2007
IEEE
98views Hardware» more  ECBS 2007»
14 years 3 months ago
A Process Module to Pre-Process Requirements for Architecting
Software architectures have a significant impact on software quality. However, building architectures is a non-trivial task. In this paper, we present a process module for pre-pro...
Matthias Galster, Armin Eberlein, Mahmood Moussavi
ASAP
2007
IEEE
144views Hardware» more  ASAP 2007»
14 years 3 months ago
A High-Throughput Programmable Decoder for LDPC Convolutional Codes
In this paper, we present and analyze a novel decoder architecture for LDPC convolutional codes (LDPCCCs). The proposed architecture enables high throughput and can be programmed ...
Marcel Bimberg, Marcos B. S. Tavares, Emil Mat&uac...
ASAP
2007
IEEE
136views Hardware» more  ASAP 2007»
14 years 3 months ago
0/1 Knapsack on Hardware: A Complete Solution
We present a memory efficient, practical, systolic, parallel architecture for the complete 0/1 knapsack dynamic programming problem, including backtracking. This problem was inte...
K. Nibbelink, S. Rajopadhye, R. McConnell
SOSE
2008
IEEE
14 years 3 months ago
Ontology for Service Oriented Testing of Web Services
This paper presents a service oriented architecture for testing Web Services. In this architecture, various parties interoperate with each other to complete testing tasks through ...
Yufeng Zhang, Hong Zhu