ATS
2001
IEEE
13 years 8 months ago
2001
IEEE
This paper develops a framework to support trace theoretic verification of timed circuits and systems. A theoretical foundation for classifying timed traces as either successes or...
ATS
2001
IEEE
13 years 8 months ago
2001
IEEE
ATS
2001
IEEE
13 years 8 months ago
2001
IEEE
Testing and diagnosis are important issues in system-onchip (SOC) development, as more and more embedded cores are being integrated into the chips. In this paper we propose a buil...
ATS
2001
IEEE
13 years 8 months ago
2001
IEEE
ATS
2001
IEEE
13 years 8 months ago
2001
IEEE
ATS
2001
IEEE
13 years 8 months ago
2001
IEEE
Testing embedded cores in a System-on-a-chip necessitates the use of a Test Access Mechanism, which provides for transportation of the test data between the chip and the core I/Os...
ATS
2001
IEEE
13 years 8 months ago
2001
IEEE
ATS
2001
IEEE
13 years 8 months ago
2001
IEEE
Test access is a major problem for core-based systemon-chip (SOC) designs. Since cores in an SOC are not directly accessible via chip inputs and outputs, special access mechanisms...
ATS
2001
IEEE
13 years 8 months ago
2001
IEEE
ATS
2001
IEEE
13 years 8 months ago
2001
IEEE