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ATS
2001
IEEE
101views Hardware» more  ATS 2001»
9 years 5 months ago
Framework of Timed Trace Theoretic Verification Revisited
This paper develops a framework to support trace theoretic verification of timed circuits and systems. A theoretical foundation for classifying timed traces as either successes or...
Bin Zhou, Tomohiro Yoneda, Chris J. Myers
ATS
2001
IEEE
172views Hardware» more  ATS 2001»
9 years 5 months ago
A Built-in Self-Test and Self-Diagnosis Scheme for Heterogeneous SRAM Clusters
Testing and diagnosis are important issues in system-onchip (SOC) development, as more and more embedded cores are being integrated into the chips. In this paper we propose a buil...
Chih-Wea Wang, Ruey-Shing Tzeng, Chi-Feng Wu, Chih...
ATS
2001
IEEE
121views Hardware» more  ATS 2001»
9 years 5 months ago
Simulation-Based Diagnosis for Crosstalk Faults in Sequential Circuits
Hiroshi Takahashi, Marong Phadoongsidhi, Yoshinobu...
ATS
2001
IEEE
137views Hardware» more  ATS 2001»
9 years 5 months ago
Compaction Schemes with Minimum Test Application Time
Testing embedded cores in a System-on-a-chip necessitates the use of a Test Access Mechanism, which provides for transportation of the test data between the chip and the core I/Os...
Ozgur Sinanoglu, Alex Orailoglu
ATS
2001
IEEE
126views Hardware» more  ATS 2001»
9 years 5 months ago
Design of an Optimal Test Access Architecture Using a Genetic Algorithm
Test access is a major problem for core-based systemon-chip (SOC) designs. Since cores in an SOC are not directly accessible via chip inputs and outputs, special access mechanisms...
Zahra Sadat Ebadi, André Ivanov
ATS
2001
IEEE
86views Hardware» more  ATS 2001»
9 years 5 months ago
Simulation and Development of Short Transparent Tests for RAM
Serge N. Demidenko, A. J. van de Goor, S. Henderso...
ATS
2001
IEEE
69views Hardware» more  ATS 2001»
9 years 5 months ago
Selecting a PRPG: Randomness, Primitiveness, or Sheer Luck?
Ismet Bayraktaroglu, Alex Orailoglu
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