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DAC
2005
ACM
10 years 16 days ago
Circuit optimization using statistical static timing analysis
In this paper, we propose a new sensitivity based, statistical gate sizing method. Since circuit optimization effects the entire shape of the circuit delay distribution, it is dif...
Aseem Agarwal, Kaviraj Chopra, David Blaauw, Vladi...
ICCAD
2000
IEEE
153views Hardware» more  ICCAD 2000»
10 years 2 months ago
Slope Propagation in Static Timing Analysis
ct Static timing analysis has traditionally used the PERT method for identifying the critical path of a digital circuit. Due to the influence of the slope of a signal at a particul...
David Blaauw, Vladimir Zolotov, Savithri Sundaresw...
IOLTS
2005
IEEE
141views Hardware» more  IOLTS 2005»
10 years 4 months ago
A Novel On-Chip Delay Measurement Hardware for Efficient Speed-Binning
With the aggressive scaling of the CMOS technology parametric variation of the transistor threshold voltage causes significant spread in the circuit delay as well as leakage spect...
Arijit Raychowdhury, Swaroop Ghosh, Kaushik Roy
ASPDAC
2006
ACM
157views Hardware» more  ASPDAC 2006»
10 years 4 months ago
Delay modeling and static timing analysis for MTCMOS circuits
- One of the critical issues in MTCMOS design is how to estimate a circuit delay quickly. In this paper, we propose a delay modeling and static timing analysis (STA) methodology ta...
Naoaki Ohkubo, Kimiyoshi Usami
ISQED
2007
IEEE
134views Hardware» more  ISQED 2007»
10 years 4 months ago
Challenges in Evaluations for a Typical-Case Design Methodology
According to the current trend of increasing variations in process technologies and thus in performance, the conservative worst-case design will not work since design margins can ...
Yuji Kunitake, Akihiro Chiyonobu, Koichiro Tanaka,...
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