Sciweavers

DFT
1997
IEEE
101views VLSI» more  DFT 1997»
13 years 9 months ago
Crosstalk Minimization in Three-Layer HVH Channel Routing
Crosstalk has become a major issue in VLSI design due to the high frequency, long interconnecting lines and small spacing between interconnects in today's integrated circuits...
Zhan Chen, Israel Koren
ISPD
1998
ACM
244views Hardware» more  ISPD 1998»
13 years 9 months ago
Analysis, reduction and avoidance of crosstalk on VLSI chips
As chip size and design density increase, coupling effects (crosstalk) between signal wires become increasingly critical to on–chip timing and even functionality. A method is pr...
Tilmann Stöhr, Markus Alt, Asmus Hetzel, J&uu...
ISPD
1999
ACM
92views Hardware» more  ISPD 1999»
13 years 9 months ago
Crosstalk constrained global route embedding
- Route Embedding, a new method for mitigating the impact of crosstalk, is presented. It modifies a set of global-route structures to prevent timing and noise-margin violations ca...
Phiroze N. Parakh, Richard B. Brown
DAC
1999
ACM
13 years 9 months ago
Crosstalk Minimization Using Wire Perturbations
We study the variation of the crosstalk in a net and its neighbors when one of its trunks is perturbed, showing that the trunk’s perturbation range can be efficiently divided i...
Prashant Saxena, C. L. Liu
ASPDAC
1999
ACM
143views Hardware» more  ASPDAC 1999»
13 years 9 months ago
Crosstalk Reduction by Transistor Sizing
In this paper we consider transistor sizing to reduce crosstalk. First, crosstalk noise dependency on wire width, wire spacing, driver and receiver sizes are discussed, and valida...
Tong Xiao, Malgorzata Marek-Sadowska
FPGA
2001
ACM
137views FPGA» more  FPGA 2001»
13 years 9 months ago
A crosstalk-aware timing-driven router for FPGAs
As integrated circuits are migrated to more advanced technologies, it has become clear that crosstalk is an important physical phenomenon that must be taken into account. Crosstal...
Steven J. E. Wilton
ITC
2003
IEEE
167views Hardware» more  ITC 2003»
13 years 10 months ago
Path Delay Test Generation for Domino Logic Circuits in the Presence of Crosstalk
A technique to derive test vectors that exercise the worstcase delay effects in a domino circuit in the presence of crosstalk is described. A model for characterizing the delay of...
Rahul Kundu, R. D. (Shawn) Blanton
PATMOS
2004
Springer
13 years 10 months ago
A Dual Low Power and Crosstalk Immune Encoding Scheme for System-on-Chip Buses
Abstract. Crosstalk causes logical errors due to data dependent delay degradation as well as energy consumption and is considered the biggest signal integrity challenge for long on...
Zahid Khan, Tughrul Arslan, Ahmet T. Erdogan
ASPDAC
2004
ACM
114views Hardware» more  ASPDAC 2004»
13 years 10 months ago
Layer assignment for crosstalk risk minimization
— In ultra-deep submicron technology, crosstalk noise is so severe that crosstalk avoidance merely in detailed routing is not adequate and it has to be considered in earlier desi...
Di Wu, Jiang Hu, Rabi N. Mahapatra, Min Zhao
GLVLSI
2005
IEEE
99views VLSI» more  GLVLSI 2005»
13 years 10 months ago
An empirical study of crosstalk in VDSM technologies
We perform a detailed study of various crosstalk scenarios in VDSM technologies by using a distributed model of the crosstalk site and make a number of key observations about the ...
Shahin Nazarian, Massoud Pedram, Emre Tuncer