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DAC
2006
ACM
10 years 24 days ago
Constraint-driven floorplan repair
Abstracting with credit is permitted. To copy otherwise, to republish, to post on servers, to redistribute to lists, or to use any component of this work in other works requires pr...
Michael D. Moffitt, Aaron N. Ng, Igor L. Markov, M...
DAC
2006
ACM
10 years 24 days ago
MARS-C: modeling and reduction of soft errors in combinational circuits
Due to the shrinking of feature size and reduction in supply voltages, nanoscale circuits have become more susceptible to radiation induced transient faults. In this paper, we pre...
Natasa Miskov-Zivanov, Diana Marculescu
DAC
2006
ACM
10 years 24 days ago
DAG-aware AIG rewriting a fresh look at combinational logic synthesis
This paper presents a technique for preprocessing combinational logic before technology mapping. The technique is based on the representation of combinational logic using And-Inve...
Alan Mishchenko, Satrajit Chatterjee, Robert K. Br...
DAC
2006
ACM
10 years 24 days ago
Leakage power reduction of embedded memories on FPGAs through location assignment
Transistor leakage is poised to become the dominant source of power dissipation in digital systems, and reconfigurable devices are not immune to this problem. Modern FPGAs already...
Yan Meng, Timothy Sherwood, Ryan Kastner
DAC
2006
ACM
10 years 24 days ago
A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy
Three-dimensional (3-D) integrated circuits have emerged as promising candidates to overcome the interconnect bottlenecks of nanometer scale designs. While they offer several othe...
Gian Luca Loi, Banit Agrawal, Navin Srivastava, Sh...
DAC
2006
ACM
10 years 24 days ago
Design tools for reliability analysis
Recent progress in EDA tools allows IC designs to be accurately verified with consequent improvements in yield and performance through reduced guard bands. This paper will present...
Zhihong Liu, Bruce McGaughy, James Z. Ma
DAC
2006
ACM
10 years 24 days ago
An efficient retiming algorithm under setup and hold constraints
In this paper we present a new efficient algorithm for retiming sequential circuits with edge-triggered registers under both setup and hold constraints. Compared with the previous...
Chuan Lin, Hai Zhou
DAC
2006
ACM
10 years 24 days ago
Optimal simultaneous mapping and clustering for FPGA delay optimization
Both technology mapping and circuit clustering have a large impact on FPGA designs in terms of circuit performance, area, and power dissipation. Existing FPGA design flows carry o...
Joey Y. Lin, Deming Chen, Jason Cong
DAC
2006
ACM
10 years 24 days ago
A new LP based incremental timing driven placement for high performance designs
In this paper, we propose a new linear programming based timing driven placement framework for high performance designs. Our LP framework is mainly net-based, but it takes advanta...
Tao Luo, David Newmark, David Z. Pan
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