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14
Voted
DATE
2006
IEEE
80views Hardware» more  DATE 2006»
13 years 10 months ago
Energy-efficient FPGA interconnect design
Despite recent advances in FPGA devices and embedded cores, their deployment in commercial products remains rather limited due to practical constraints on, for example, cost, size...
Maurice Meijer, Rohini Krishnan, Martijn T. Benneb...
DATE
2006
IEEE
88views Hardware» more  DATE 2006»
13 years 10 months ago
Using conjugate symmetries to enhance gate-level simulations
State machine based simulation of Boolean functions is substantially faster if the function being simulated is symmetric. Unfortunately function symmetries are comparatively rare....
Peter M. Maurer
DATE
2006
IEEE
69views Hardware» more  DATE 2006»
13 years 10 months ago
A new approach to compress the configuration information of programmable devices
Maurizio Martina, Guido Masera, Andrea Molino, Fab...
DATE
2006
IEEE
110views Hardware» more  DATE 2006»
13 years 10 months ago
Top-down heterogeneous synthesis of analog and mixed-signal systems
A new approach for automated synthesis of analog and mixed-signal systems is presented. The heterogeneous genetic optimization strategy starts from a functional description and ev...
Ewout Martens, Georges G. E. Gielen
DATE
2006
IEEE
91views Hardware» more  DATE 2006»
13 years 10 months ago
Is "Network" the next "Big Idea" in design?
As the complexity of nowadays systems continues to grow, we are moving away from creating individual components from scratch, toward methodologies that emphasize composition of re...
Radu Marculescu, Jan M. Rabaey, Alberto L. Sangiov...
DATE
2006
IEEE
94views Hardware» more  DATE 2006»
13 years 10 months ago
Procrastinating voltage scheduling with discrete frequency sets
This paper presents an efficient method to find the optimal intra-task voltage/frequency scheduling for single tasks in practical real-time systems using statistical workload in...
Zhijian Lu, Yan Zhang, Mircea R. Stan, John Lach, ...
DATE
2006
IEEE
94views Hardware» more  DATE 2006»
13 years 10 months ago
Reuse-based test access and integrated test scheduling for network-on-chip
In this paper, we propose a new method for test access and test scheduling in NoC-based system. It relies on a progressive reuse of the network resources for transporting test dat...
Chunsheng Liu, Zach Link, Dhiraj K. Pradhan
DATE
2006
IEEE
125views Hardware» more  DATE 2006»
13 years 10 months ago
Crosstalk-aware domino logic synthesis
We propose a logic synthesis flow which utilizes the functionality of circuit to synthesize a domino-cell network which will have more wires crosstalk-immune to each other. For t...
Yi-Yu Liu, TingTing Hwang