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DATE
2006
IEEE
78views Hardware» more  DATE 2006»
13 years 10 months ago
STAX: statistical crosstalk target set compaction
This paper presents STAX, a crosstalk target set compaction framework to reduce the complexity of the crosstalk ATPG process by pruning non-fault-producing targets. In general, ex...
Shahin Nazarian, Massoud Pedram, Sandeep K. Gupta,...
DATE
2006
IEEE
124views Hardware» more  DATE 2006»
13 years 10 months ago
Cell delay analysis based on rate-of-current change
Abstract - A cell delay model based on rate-of-currentchange is presented, which accounts for the impact of the shape of the noisy waveform on the output voltage waveform. More pre...
Shahin Nazarian, Massoud Pedram
DATE
2006
IEEE
88views Hardware» more  DATE 2006»
13 years 10 months ago
Temporal partitioning for image processing based on time-space complexity in reconfigurable architectures
Temporal partitioning techniques are useful to implement large and complex applications, which can be split into partitions in FPGA devices. In order to minimize resources, each o...
Paulo Sérgio B. do Nascimento, Manoel Euseb...
DATE
2006
IEEE
109views Hardware» more  DATE 2006»
13 years 10 months ago
A methodology for mapping multiple use-cases onto networks on chips
A communication-centric design approach, Networks on Chips (NoCs), has emerged as the design paradigm for designing a scalable communication infrastructure for future Systems on C...
Srinivasan Murali, Martijn Coenen, Andrei Radulesc...
DATE
2006
IEEE
134views Hardware» more  DATE 2006»
13 years 10 months ago
ASIP-based multiprocessor SoC design for simple and double binary turbo decoding
This paper presents a new multiprocessor platform for high throughput turbo decoding. The proposed platform is based on a new configurable ASIP combined with an efficient memory a...
Olivier Muller, Amer Baghdadi, Michel Jéz&e...
DATE
2006
IEEE
77views Hardware» more  DATE 2006»
13 years 10 months ago
Proven correct monitors from PSL specifications
Katell Morin-Allory, Dominique Borrione
DATE
2006
IEEE
66views Hardware» more  DATE 2006»
13 years 10 months ago
Power/performance hardware optimization for synchronization intensive applications in MPSoCs
This paper explores optimization techniques of the synchronization mechanisms for MPSoCs based on complex interconnect (Network-on-Chip), targeted at future powerefficient system...
Matteo Monchiero, Gianluca Palermo, Cristina Silva...
DATE
2006
IEEE
142views Hardware» more  DATE 2006»
13 years 10 months ago
Physical-aware simulated annealing optimization of gate leakage in nanoscale datapath circuits
For CMOS technologies below 65nm, gate oxide direct tunneling current is a major component of the total power dissipation. This paper presents a simulated annealing based algorith...
Saraju P. Mohanty, Ramakrishna Velagapudi, Elias K...
DATE
2006
IEEE
122views Hardware» more  DATE 2006»
13 years 10 months ago
Power analysis of mobile 3D graphics
— The world of 3D graphics, until recently restricted to high-end workstations and game consoles, is rapidly expanding into the domain of mobile platforms such as cellular phones...
Bren Mochocki, Kanishka Lahiri, Srihari Cadambi
DATE
2006
IEEE
105views Hardware» more  DATE 2006»
13 years 10 months ago
Optical routing for 3D system-on-package
Abstract— Optical interconnects enable faster signal propagation with virtually no crosstalk. In addition, wavelength division multiplexing allows a single waveguide to be shared...
Jacob R. Minz, Somaskanda Thyagaraja, Sung Kyu Lim