DATE
2006
IEEE
13 years 11 months ago
2006
IEEE
In this paper we analyze the test power of SRAM memories and demonstrate that the full functional precharge activity is not necessary during test mode because of the predictable a...
DATE
2006
IEEE
13 years 11 months ago
2006
IEEE
Because of its excellent bit-error-rate performance, the Low-Density Parity-Check (LDPC) algorithm is gaining increased attention in communication standards and literature. The ne...
DATE
2006
IEEE
13 years 11 months ago
2006
IEEE
Pseudorandom test techniques are widely used for measuring the impulse response (IR) for linear devices and Volterra kernels for nonlinear devices, especially in the acoustics dom...
DATE
2006
IEEE
13 years 11 months ago
2006
IEEE
We present a modular and scalable approach for automatically extracting actual performance information from a set of FPGA-based architecture topologies. This information is used d...
DATE
2006
IEEE
2006
IEEE
Design and implementation of a rendering algorithm in a SIMD reconfigurable architecture (MorphoSys)
13 years 11 months ago
In this paper we analyze a 3D image rendering algorithm and the different mapping schemes to implement it in a SIMD reconfigurable architecture. 3D image render is highly computat...
DATE
2006
IEEE
13 years 11 months ago
2006
IEEE
In recent years, Assertion-Based Verification is being widely accepted as a key technology in the pre-silicon validation of system-on-chip(SOC) designs. The System Verilog langua...
DATE
2006
IEEE
13 years 11 months ago
2006
IEEE
Practitioners of formal property verification often work around the capacity limitations of formal verification tools by breaking down properties into smaller properties that ca...
DATE
2006
IEEE
13 years 11 months ago
2006
IEEE
Scheduling is an important step in high-level synthesis (HLS). In our tool, we perform scheduling in two steps: coarse-grain scheduling, in which we take into account the whole co...
DATE
2006
IEEE
13 years 11 months ago
2006
IEEE
This paper describes a fast-lock mixed-mode delaylocked loop (MMDLL) for wide-range operation and multiphase outputs. The architecture of the proposed DLL uses the mixed-mode time...
DATE
2006
IEEE
13 years 11 months ago
2006
IEEE
Much research has focused on power conservation for the processor, while power conservation for I/O devices has received little attention. In this paper, we analyze the problem of...